Alexander Fell

Research Interests

I am interested into multiple areas such as Coarse Grain Reconfigurable Architectures (CGRAs), Network-on-Chip and Embedded Systems which I briefly describe below. If you are interested in a project in one of these areas, please read the section projects before applying.

Coarse Grain Reconfigurable Architectures (CGRAs)

Coarse Grain Reconfigurable Architectures (CGRAs) are a fairly new area of research. It is a architecture which consists of two major parts: Compute Elements which are able to execute arithmetical and logical operations by utilizing ALUs, and an interconnect which establishes communications between the Compute Elements transporting results, operands and control information. The workflow usually starts from a data flow graph (DFG) which represents the algorithm to be executed on the CGRA. In a first step this DFG is converted into a graph in which the nodes represent the Compute Elements (i.e. the operations to be performed) and the edges the interconnections (i.e. the dependencies among the operations). This converted DFG is then loaded onto the CGRA.

This kind of architecture has major advantages over General Purpose Processors, ASICs and FPGAs:

  1. It is reprogrammable and the algorithm can be changed, after the CGRA has been deployed.
  2. It is coarse grained compared to FPGAs which are programmed on a bit level, since CGRAs accept instructions as smallest grain. Hence high level languages such as C can be used to implement the desired algorithm.
  3. Due to scalability (a CGRA can have Compute Elements in the order of hundreds) and massive parallelism, it is faster than General Purpose Processors.

However there are also some drawbacks which I focus on:

  1. The graph conversion from the DFG to a graph than can be executed on the CGRA, cannot be computed on a polynomial time. Hence heuristics are used which need to be tested extensively and proven mathematically.
  2. To ensure scalability the interconnect is usually a Network-on-Chip (see below). It turns out that this Network can be a major bottleneck not able to deliver the operands to the Compute Element and transporting away the results fast enough.

Network-on-Chip (NoC)

A bus system uses a shared medium and a global controller, which arbitrates among the attached units that wishes to transmit data. A Network-on-Chip (NoC) is a distributed system in which each node could be considered to be an intersection and the decision which direction incoming data is forwarded to, is taken here. The figure on the right shows an example of a hexagonal (or triangular, thick and thin lines) and honeycomb (thick lines only) NoC topology including the absolute addresses of its nodes. Since the data is forwarded or also called "routed" the nodes are called routers. Apart from this ability to accept data from multiple sources at the same time, the other advantage of an NoC is its scalability supporting more simultaneous communication pairs than a bus system.

During my PhD work, an NoC called RECONNECT, has been implemented, which can be flexibly configured leaving design choices with the developer. Among other features this NoC supported wormhole routing, different topologies including different routing algorithms for all kind of scenarios.

Embedded Systems

Recently my research interest also includes Embedded Systems, especially in the area of remote sensing in which a long battery life in extreme weather conditions is essential. This necessity requires to think out of the box by, for instance, "misusing" sensors to gather other information that they were originally built for. These systems are then tested and deployed by the Wildlife Institute of India.